The present invention relates to a semiconductor integrated circuit device, and is applicable to a semiconductor integrated circuit device provided with an A/D converter, for example.
Some A/D converter is configured with an A/D conversion unit which converts an analog signal into a digital signal, and a digital correction unit which performs digital correction to the output of the A/D conversion unit and outputs the corrected output as an A/D conversion result of the A/D converter. The A/D converter which performs the digital correction using the A/D conversion unit and the digital correction unit in this way functions as an A/D converter with high speed, high accuracy, and low power consumption. Hereinafter, analog to digital conversion is called A/D conversion and an analog to digital converter is called an A/D converter.
An A/D converter which performs digital correction is disclosed by Non Patent Literature 1. The A/D converter disclosed by Non Patent Literature 1 is configured with one A/D conversion unit and two digital correction units, to perform the digital correction. The A/D conversion unit is of a charge redistribution type and performs successive approximation. The A/D conversion unit performs A/D conversion twice to the same sample voltage. After correcting the two A/D conversion results by each digital correction unit, a correction coefficient is searched for on the basis of the difference of these outputs.    (Non-Patent Literature 1) W. Liu et al; “A 12b 22.5/45 MS/s 3.0 mW 0.059 mm2 CMOS SARADC achieving over 90 dB SFDR,” IEEE 2010 International Solid-State Circuits Conference, pp. 380-381, February 2010.